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[VHDL-FPGA-Verilog] u-uart

Description: 一个可综合的串并转换接口verilog源代码-a comprehensive series of conversion and interface Verilog source code
Platform: | Size: 5120 | Author: 李文文 | Hits:

[VHDL-FPGA-Verilog] uart-verilog-vhdl

Description: 拿verilog和vhdl编写的串口通信代码(可综合)-with vhdl and verilog prepared by the serial communication code (synthesis)
Platform: | Size: 294912 | Author: 刘索山 | Hits:

[VHDL-FPGA-Verilog] uart_core_vhdlORverilog

Description: 串uart的vhdl，verilog，lattic实现原码里面有四个文件,分别UART 源码 (lattice version)\uart 源码 (Verilog)\uart 源码 (VHDL)\uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice version) \ uart source (Verilog) \ uart source (VHDL) \ uart16550.tar
Platform: | Size: 294912 | Author: efly | Hits:

[VHDL-FPGA-Verilog] S6_VGA_change

Description: verilog源代码，quartusII工程。程序实现VGA时序。控制VGA显示器输出图形。在quartusII中客直接运行，-Verilog source code, quartusII works. Procedures to achieve VGA timing. VGA graphics display control output. QuartusII in the direct run-off,
Platform: | Size: 2572288 | Author: 李晨 | Hits:

[assembly language] lcd_module

Description: verilog code which receive from uart RX and then output to lcd text display.
Platform: | Size: 2048 | Author: 蔡俊仪 | Hits:

[Other Embeded program] UART

Description: 一个通用串口的verilog源程序，包含发送和接收模块-A universal serial Verilog source code, including sending and receiving modules
Platform: | Size: 53248 | Author: typhooncome | Hits:

[VHDL-FPGA-Verilog] Fusion_UART

Description: UART实验Verilog HDL代码，用于FPGA-UART experimental Verilog HDL code for FPGA
Platform: | Size: 3072 | Author: 张猛蛟 | Hits:

[VHDL-FPGA-Verilog] ethernet_tri_mode_rtl.tar

Description: verilog实现的异步UART代码，包括发送模块、接收模块，波特率可配置，另附PC机的c代码-Verilog realize asynchronous UART code, including the transmission module, receiver module, the baud rate can be configured, an additional PC-c code
Platform: | Size: 38912 | Author: | Hits:

[Com Port] uart

Description: this a Uart source code using Verilog.
Platform: | Size: 10240 | Author: Daniel Zhang | Hits:

[Com Port] uart(Verilog)

Description: RS232的verilog源代码,如果需要的可以-RS232 of Verilog source code, if necessary can be
Platform: | Size: 10240 | Author: 陈强 | Hits:

[VHDL-FPGA-Verilog] uart(Verilog)

Description: uart异步串口通信协议的源代码，用vhdl语言编写，并且有完整得测试文件-UART asynchronous serial communication protocol source code, using VHDL language, and may have a complete test file
Platform: | Size: 10240 | Author: 阿军 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 串口通讯 verilog CPLD EPM1270 源代码-Serial Communication verilog CPLDEPM1270 source code
Platform: | Size: 56320 | Author: 韩思贤 | Hits:

[Com Port] UART

Description: 内含有完整的UART代码，包括发送和接受，且有testbench，可以直接仿真调试-Contain complete UART code, including send and receive and there testbench, can directly Simulation debugging
Platform: | Size: 9216 | Author: 李佳 | Hits:

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[VHDL-FPGA-Verilog] u-uart

[VHDL-FPGA-Verilog] uart-verilog-vhdl

[VHDL-FPGA-Verilog] uart_core_vhdlORverilog

[VHDL-FPGA-Verilog] S6_VGA_change

[assembly language] lcd_module

[Other Embeded program] UART

[VHDL-FPGA-Verilog] Fusion_UART

[VHDL-FPGA-Verilog] ethernet_tri_mode_rtl.tar

[Com Port] uart

[Com Port] uart(Verilog)

[VHDL-FPGA-Verilog] uart(Verilog)

[VHDL-FPGA-Verilog] UART

[Com Port] UART

[VHDL-FPGA-Verilog] fpga_uartrw

[VHDL-FPGA-Verilog] mini-uart

[Software Engineering] lab3

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] uart-code-Verilog

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] uart

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